FM Radio Receiver in SystemVerilog
For my final project in CE 387: Real-Time Digital Systems Design and Verification with FPGAs, I designed and verified a complete stereo FM radio receiver in SystemVerilog based on a provided C reference model. The design implements the full FM receive chain, including complex channel filtering, FM demodulation, pilot-tone recovery, stereo decoding, deemphasis filtering, and audio reconstruction. A reusable streaming architecture with parameterized FIR filters, FIFOs, and fixed-point arithmetic was developed and optimized to meet FPGA resource and timing constraints. Verification was performed using a custom UVM environment that compared RTL outputs against a software-generated reference over 100,000 stereo output vectors with 100% functional coverage and zero mismatches. Through iterative architectural optimizations, including multi-cycle datapaths, pipelining, and retiming, the final design achieved a synthesized operating frequency of 136.8 MHz while remaining within the target FPGA resource limits.
